System and method of clocking an ip core during a debugging operation

ABSTRACT

According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.

The present invention relates to a system and a method of clocking an IPcore during a debugging operation.

In the design of integrated circuits, there is an increasing demand foremulation and verification tools. Hardware-based verification solutionshave been around for years in two different embodiments: acceleratorsand emulators. Useful tools in emulation systems are so-called IP-Xpresskits which are emulation-ready kits for concurrent hardware and softwareverification of processor-based systems. Such IP-Xpress kits usemicroprocessor or DSP chips, mounted onto a printed-circuit-board toprovide the functionality of the device to be connected to a designmapped into the emulator, and the kits consist of a board andHDL-wrapper files.

All processor-type IP cores require some external clock source. Hence,one or more clock signals are provided to the IP-Xpress boards. Theclocks are provided either directly from the internal clock generatorsof the emulator or they may be driven from the design loaded onto theemulator.

Another way of providing clock to an IP core is by using a clockoscillator mounted onto the IP-Xpress board. In this case any frequencycan be applied, i.e. there are no maximum clock frequency constraintsdue to the emulation system.

A key advantage of an IP-Xpress kit is to provide a fast running systemverification environment in which application software is running on theIP core and this stimulating the design mapped to the emulator. In caseof faulty system behaviour, the cause for this could either be in theapplication software or in the design (provided the IP core isfunctioning correctly). In order to identify the erroneous component ofthe system both the application software as well as the design has to bedebugged. This can be done most conveniently when the hardware andsoftware are stopped synchronously. On the one hand, this gives a goodcorrelation between the design's status and the actual softwareexecution, and on the other hand it enables to interrogate all resourcesof the design mapped onto the emulator system. This may mean, however,that the emulator clocks are stopped. In case the IP core is clocked bya clock generated by the emulator system, this would mean that the IPcore is not clocked anymore. Hence, the software debugger would notnecessarily work and as a result the resources of the software executionwere not visible and a full system debugging would not be possible.

It is the object of the present invention to provide a system and amethod of clocking an IP core during a debugging operation. This objectis achieved with the features of the claims.

In order to achieve this object, according to the present invention, theclock generation for the IP core when entering the system debugging modeis implemented on the IP-Xpress board itself. There is provided a clockoscillator and a switching means, and the switching means switches tothe clock oscillator provided on the IP-Xpress board as soon as thesystem debug mode is entered. In order to initiate the switchingoperation, the switching means monitors signals specific to the IP corewhich indicate a breakpoint, e.g., EMU0/1 in case of TI C6x DSPs, and ifthese indicate that a breakpoint has been entered, the clock output ofthe switching means is driven from the clock oscillator. Hence, the IPcore is continuously clocked even when the clocks of the emulator systemare stopped. Furthermore, the software debugger is still functional inits system debug mode and all IP core internal resources and thesoftware execution status can be investigated.

Upon leaving the system debug mode, the switching means is signalled toswitch back to the clocks of the emulator system, and the systemexecution can continue in its normal operational mode.

The present invention will now be described with reference to thefigure. The figure shows a preferred embodiment of the present inventioncomprising a switching means 1. Connected to the switching means is aclock oscillator 2. On the left of the figure there are shown twopossible clock sources for the normal operation of the emulator system.These clock signals are driven through the backplane of the emulatorsystem onto the IP-Xpress board. The signal gpc2i_clkin is a drivenclock from the design, and gpc2i_j17_clkin is a clock directly from thegenerator of the emulator. Depending on the select signal supplied tothe multiplexer 3 either of these clocks is provided to the IP core. Forexample, the IP core is a DSP. The clock oscillator 2, the switchingmeans 1 and the signals indicating a breakpoint form the clock generatorwhen entering the breakpoint mode. The output of the switching means isa clock signal that clocks the IP core.

During normal operation of the emulator system, the switching meansfeeds a “regular” clock through its output. When the system debug modeis entered, the switching means switches from this “regular” clock tothe clock oscillator provided on the IP-Xpress board.

The following code fractions demonstrate how the switching to the clockoscillator can be implemented inside the switching means. ---------------------------------------------------- -- Memorizebreakpoint ( ie: !EMU0 or !EMU1) ---------------------------------------------------- process(RESET,EMU_LATCH_RST, OSC_CLK) begin if (RESET = ′0′ or EMU_LATCH_RST = ′0′ )then emu_trigger <= ′0′; elsif rising_edge(OSC_CLK) then if (EMU0 = ′0′or EMU1 = ′0′ or emu_trigger = ′1′) then emu_trigger <= ′1′; elseemu_trigger <= ′0′; end if; end if; end process; ---------------------------------------------------- -- Latch emu_triggerwith the falling edge of CLKIN1 ---------------------------------------------------- process(RESET,CLKIN1) begin if (RESET = ′0′) then clk_sel1 <= ′0′; elsiffalling_edge(CLKIN1) then clk_sel1 <= emu_trigger; end if; end process;-- -------------------------------------------------- -- Select theright clock for int_clk_for dsp1. -- When the emulator is running selectCLKIN1 -- else, when a breakpoint occurs, select OSC_CLK -- so that theconnection with the software debugger -- is not lost ---------------------------------------------------- process (CLKIN1,OSC_CLK, clk_sel1) begin case clk_sel1 is when ′0′ => int_clk_for_dsp1<= CLKIN1; when ′1′ => int_clk_for_dsp1 <= OSC_CLK; when others =>int_clk_for_dsp1 <= ′0′; end case; end process;

1. A method of clocking an IP core during a debugging operation,characterized by switching from a clock used for testing a design mappedonto an emulator to a clock oscillator or any free-running clock source.2. The method of claim 1, wherein said switching is to said clockoscillator, which is provided on an IP-Xpress board.
 3. The method ofclaim 1, wherein the clock used for testing the design is either: a) aclock sourced from the design mapped into the emulator b) a clocksourced directly from the emulators clock generator circuits c) a clockoscillator locally mounted on the IP-Xpress daughter board, or any freerunning clock source
 4. The method of claim 1, comprising the step ofmonitoring signals specific to the IP core which indicate a breakpointin order to detect the breakpoint.
 5. The method of claim 4, whereinsaid switching is performed upon detecting that the breakpoint has beenentered.
 6. The method of claim 1, wherein the IP core is amicroprocessor or a DSP.
 7. A system for clocking an IP core during adebugging operation, comprising switching means; a clock oscillator orany free-running clock source; and control means for sending a controlsignal to the switching means when the debugging operation is started,for switching the switching means to the clock oscillator or anyfree-running clock source.